
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   22:45:06 02/08/2011
-- Design Name:   MAIN_CONTROtop
-- Module Name:   E:/main_control/tb_main_alu_rom.vhd
-- Project Name:  main_control
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: MAIN_CONTROtop
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_main_alu_rom_vhd IS
END tb_main_alu_rom_vhd;

ARCHITECTURE beh OF tb_main_alu_rom_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT MAIN_CONTROtop
	PORT(
		Reset : IN std_logic;
		Clk : IN std_logic;
		--ROM_Data : IN std_logic_vector(11 downto 0);
		DMA_RQ : IN std_logic;
		DMA_READY : IN std_logic;          
		--ROM_Addr : OUT std_logic_vector(11 downto 0);
		RAM_Addr : OUT std_logic_vector(7 downto 0);
		RAM_CS : OUT std_logic;
		RAM_Write : OUT std_logic;
		RAM_OE : OUT std_logic;
		DMA_ACK : OUT std_logic;
		SEND_comm : out  std_logic
		--Databus   : inout  std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL Reset :  std_logic := '0';
	SIGNAL Clk :  std_logic := '0';
	SIGNAL DMA_RQ :  std_logic := '0';
	SIGNAL DMA_READY :  std_logic := '0';
	--SIGNAL ROM_Data :  std_logic_vector(11 downto 0) := (others=>'0');

	--Outputs
	--SIGNAL ROM_Addr :  std_logic_vector(11 downto 0);
	SIGNAL RAM_Addr :  std_logic_vector(7 downto 0);
	SIGNAL RAM_CS :  std_logic;
	SIGNAL RAM_Write :  std_logic;
	SIGNAL RAM_OE :  std_logic;
	SIGNAL DMA_ACK :  std_logic;
	signal SEND_comm: std_logic;
	--signal databus: std_logic_vector(7 downto 0);
BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: MAIN_CONTROtop PORT MAP(
		Reset => Reset,
		Clk => Clk,
		--ROM_Data => ROM_Data,
		--ROM_Addr => ROM_Addr,
		RAM_Addr => RAM_Addr,
		RAM_CS => RAM_CS,
		RAM_Write => RAM_Write,
		RAM_OE => RAM_OE,
		DMA_RQ => DMA_RQ,
		DMA_ACK => DMA_ACK,
		DMA_READY => DMA_READY,
		SEND_comm=> SEND_comm
		--Databus=>Databus
	);

	Reset <= '0', '1' after 10 ns;
	
	clking: PROCESS
	BEGIN
	
		CLK <= '1', '0' after 25 ns;
		wait for 50 ns;
		
	END PROCESS clking;
	
	
	tb : PROCESS
	BEGIN

		--Databus <= "11010111";
      Reset   <= '1'; --after 10 ns ;
      --DMA_RQ  <= '1', '0' after 12 us, '1' after 18 us;-- '0' after 20 us;
      --DMA_READY <= '0', '1' after 10 us;

      wait for 50 us;
      wait;
	END PROCESS;

END beh;
